招聘城市:上海
…cost
· Responsible for Testing circuits Design and super high layers PCB design for high complexity ATE device interface board correspond to various device testing, eg. Mobile application processor, High performance computer, AI, RF etc.
· Responsible for scheme selection of a SUBSTRATE/MLO design in wafer testing, research for low Cost of Test scheme (considering TDE, Skip DIE, substrate stack-up)
· Responsible for power integrity (PI) and signal integrity (SI) simulation at board level or system level, frequency domain or time domain to ensure HW product performance at design stage
· Implement complex mechanical design/simulation, cable design, thermal evaluation by collaborating with PCB design to achieve premium quality in hardware solution according to customer device testing ultimate challenges.
· Responsible for global end to end hardware project management to ensure best quality and on time delivery
ü Device testing requirement assessment and Feasibility study
ü Risk analysis and mitigation planning
ü Schedule…
…cost
· Responsible for Testing circuits Design and super high layers PCB design for high complexity ATE device interface board correspond to various device testing, eg. Mobile application processor, High performance computer, AI, RF etc.
· Responsible for scheme selection of a SUBSTRATE/MLO design in wafer testing, research for low Cost of Test scheme (considering TDE, Skip DIE, substrate stack-up)
· Responsible for power integrity (PI) and signal integrity (SI) simulation at board level or system level, frequency domain or time domain to ensure HW product performance at design stage
· Implement complex mechanical design/simulation, cable design, thermal evaluation by collaborating with PCB design to achieve premium quality in hardware solution according to customer device testing ultimate challenges.
· Responsible for global end to end hardware project management to ensure best quality and on time delivery
ü Device testing requirement assessment and Feasibility study
ü Risk analysis and mitigation planning
ü Schedule…